Smartphones and Tablets Thirst for Bandwidth

The explosive growth in portable devices over the past decade has left manufactures in a quandary over how to add memory to their products that meet several criteria:

• High capacity
• Low cost
• Low power
• High bandwidth

The Flash storage industry has provided capacity to support large multimedia files such as video, music and photos. Accompanying the technology improvements have been standards developments that allow multi-tasking of applications and faster web browsing. The JEDEC eMMC standard evolved from 4.1 to the current 4.5 revision. The standards also have allowed applications to migrate from parallel bus interface to serial differential transmission for higher throughput.

A separate industry consortia, the Mobile Industry Processor Interface (MIPI), is developing a high-performance, serial I/O standard for data transfers between portable embedded devices such as display, cameras and application co-processors. As performance for both specifications improved both standards it became clear that there was need for only one. In 2010, both and MIPI and JEDEC adopted the UFS as the common data transfer protocol for mobile systems.

Universal Flash Storage (UFS) Standard

The UFS standard is designed to offer a fast, reliable and simple means of supporting storage requirements in portable applications such as smart phones. UFS represents the next generation in Flash storage standards. It supports both embedded and removable card applications.

The standard features low power consumption improving battery life through efficient and smart power management and reduced component count. UFS performance varies according to the Gear or version. The current UFS Gear 1 offers 1.5Gbps while Gear 2 will have 3Gbps, and Gear 3 will handle up to 6Gbps.

The standard offers power/performance tradeoffs in the form of different power states of the M-PHY. When the device is not being used in data transfers it shifts its state among seven possible states. Each state uses less power according to the number states traversed to get to the higher power consuming data transfer state. UFS uses a 50 MHz clock and differential signaling for its serial transfers of up to four lanes. It supports both Pulse Width Modulation (PWM) and Non-Return to Zero (NRZ) data encoding.

Live Webinar

Register to Join a live Webinar on UFS presented by Arasan Chip Systems on Feb 28 6PM PST or Feb 29 10AM PST

Leave a Reply