NAND Flash – Multipurpose Memory Goes Mainstream


NAND Flash memory is set to pass DRAM in the semiconductor. Apple is the primary driver and Apple products will consume the bulk of tablet and smartphone NAND ICs. At the same time the number of applications that leverage the density, performance and non-volatile benefits of NAND Flash will continue to increase.

NAND Flash is used to replace (HDD) hard disk drives, provide cache for HDD, or extend the size of main (DRAM) memory.  End applications extend from consumer to the enterprise in segments such as:

  • Consumer tablet and ultrabook computing
  • Cache storage in transaction processing centers (– e.g. banking, payroll, etc.)
  • I/O performance in virtualized server farms
  • Secure backup for failsafe applications
  • Optimizing footprint (power and space of HDD vs. SDD based on IOPS)

The controller and interface requirements for these cover a wide range of technologies. In the case of DRAM backup in server failsafe applications for instant wake up and emergency power-down protection, sophisticated wear leveling is not required.  For mass storage requirements, wear leveling and error correction codes (ECC) are critical for data integrity. The latest generation of high density multilevel cell (MLC) NAND Flash achieve up to 128Gbit in a single IC using 20nm process technology.[1]  The tradeoff for achieve high density with MLC is lower program/erase cycles and higher bit error rates, necessitating complicated cyclic codes such as Reed-Solomon (R/S) or Bose-Chaudhuri-Hocquenghem (BCH) to increase the correction capability.

Most suppliers of NAND Flash memory have adopted the ONFI (Open NAND Flash Interface) standard, which defines package pin out, signaling and interface requirements.  The latest ONFI standard is 3.0 released in March 2011.   ONFI 3.0 provides NVDDR 2.0 (also termed toggle 2) which provides up to 400M transfers per sec. This is a three-fold increase over DDR 1 (133MTps) and a ten-fold increase over SDR (40MTps).  Toggle 2 utilizes a “clock-less” mode whereby transfers are “toggled” by the data strobe (DQS).  The high data rate is supported with on-die termination and 1.8V I/O signal levels.  ONFI 3.0 also defines a reduced chip enable protocol to simplify SSD controller design.

Arasan Chip Systems provides a full ONFI 3.0 compliant NAND Flash PHY and control logic suitable for ARM based controllers in applications ranging from consumer tablets, ultrabooks and enterprise server SSD. ONFI 3.0 is backward compatible to all previous ONFI standards supporting SLC and MLC NAND Flash. A typical SSD has an ARM based NAND controller talking to many NAND flash via ONFI interface.   And, the other side of this NAND controller is plugged into the PCIe bus or SATA bus to communicate with the host CPU.  The signal flow goes from an Intel CPU to PCIe bus on the mother board to PCIe receiver on the SSD drive connected to an ARM based NAND controller interfacing to ONFI NAND controller and a set of NAND Flash ICs. Arasan’s patent-pending BCH ECC implementation uses an inversionless Berlekamp-Massey algorithm and a parallel Chien search algorithm. Up to 64b or more of error correction is provided.

 

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