NAND Flash is the nonvolatile memory behind SSD, mobile computing devices and mobile appliances (such as phones and cameras). Flash technology is the mainstream storage solution for mobile – and mobile is growing dramatically. Some analysts predict tablet shipments will eclipse PC shipments by 2016.
Why Benchmarking matters
Tablet computers and smartphones place increasing demands on NAND Flash device features – capacity, cost and bandwidth. But providing this requires a complex combination of electronic and software development. As a result benchmarking NAND Flash at the component and system level is critical to successful product design.
Benchmark testing spans a wide range of factors such as the device controller implementation, the host interface standard (SD, eMMC, UFS), type of NAND technology (SLC, MLC, TLC), device drivers and file systems and the application requirements, e.g. sequential, random, read-write, etc.
NAND Flash Technology is Tricky
NAND Flash cells are read at the page level and erased at the block level. Cells must be erased before programmed. For example, a 16Gb NAND Flash from Micron , uses a 4KB page and a 512KB block. Every time data is written to a block the entire block is erased. Internally valid is copied to available blocks. In effect an external write will produce multiple internal writes.
Block management accomplishes several tasks related to translation of logical addresses to physical addresses including bad block tagging, dynamic buffering for performance, and garbage collection. This function may be implemented in a Flash Translation Layer (FTL) in firmware or a Flash File System (FLS) running on the host.
Wear leveling manages the local to physical mapping so that erase/write cycles are distrusted evenly over the entire range of the memory array to optimize the life of the device. Typically this is implemented in controller FTL where the P/E cycle count is known. New approaches based on BER optimization are emerging. 
Some error recovery can be implemented in the controller command logic (with extra P/E cycles) for read / write disturb errors when adjacent (unintended) cells voltage levels shift from I/O activity. Other errors such as voltage shift from alpha particles injection rely on ECC to resolve.
Error correction code (ECC) solutions are based on Hamming, Reed-Solomon, BCH  and LDPC. Hardware solutions scale in complexity with the NAND block size and the error correction requirements. SInce soft errors scale with shrinking NAND process geometry, the hardware costs of ECC are increasing. Low Parity Density Codes, use statistical algorithms implemented in firmware to reduce block-level BER with less integrated circuit area. 
Signal Processing Optimization
Beyond merely correcting errors, signal processing recovers correct bits by analyzing multiple read voltages. Integrating signal processing, ECC and FTL into the device controller, e.g. “managed NAND” by Anobit . NAND device suppliers, e.g. SK Hynix and Micron, are integrating control functionality like ECC and signal processing onto the NAND die or dedicated controller die in the NAND package. [6,21]
Controller design is intimately tied to the NAND device. The degree is only increasing as NAND technology shrinks and NAND devices grow in complexity and density. Mobile Storage devices may exhibit dramatically different results depending on price and application requirements.
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Written by Sam Beal