Most any digital system will require state machines to control the operation and implement algorithms. State machines are easily enough to write manually, but because they tend to require much iteration during development the frequent modifications can be tiresome and error prone. In addition, documenting the functionality becomes a chore as each iteration must be updated.
In the mid-nineties a solution appeared that seemed to address iterating and documenting state machines. A small company offered State CAD, a tool that enabled graphical entry of state machines. Along with the ease of graphical entry the tool compiled to RTL so the results could be synthesized to ant technology.
Graphical entry allows designers to see exactly what the logic does without having to pour over lines of code. Moreover, graphic entry is faster and less error prone than manual coding. Best of all, the graphic and code are always identical because one is the child of the other.
A few years after its introduction, the tool was acquired by Xilinx and added to the tool suite. It remained available without cost as part of the Xilinx suite and, best of all, technology independent.
The tool, however, disappeared after the ISE 10.1 release years ago for reasons that are obscure. For engineers who are familiar with the benefits of State CAD an internet search and a bit of luck will uncover its location. But those unfortunates who have never been introduced to the benefits of graphical entry may remain mired in their tedious ways.
While there are other tools available that have similar capabilities, none reputedly offer RTL outputs nor are they complementary.
The State CAD UI is straightforward and examples of its use abound. For example, see: http://ece.wpi.edu/~rjduck/state_cad_tutorial.pdf. In a nutshell, you select the circle icon for adding states and the arrow icon for transitions. You can add outputs to states and conditions to the transitions. There are countless other features.
The tool has a page for compile options that lets users select language (Verilog or VHDL) and other parameters such as to optimize for speed vs. size, or whether to register outputs. Errors show up at compile time and the tool offers suggestions for corrections.
Xilinx does not maintain State CAD and it is aging. One drawback in using it with Windows 7 in 64-bit mode causes a missing MSVC71.dll error. My attempts to circumvent the DLL problem were not fruitful.
Perhaps an enterprising Windows guru can give us a DLL workaround. Better yet, persuade Xilinx management to sell the tool for a dollar so that it may be made available for engineers to come. Otherwise, I fear its usage will in time will be swamped by operating system improvements.
Written by Dennis McCarty